The present invention relates to a dynamic RAM, i.e., a dynamic type random access memory and, more particularly, to a technique in which a reading reference voltage is generated by a full-size dummy cell.
A 1-bit memory cell in a dynamic RAM is composed, for example, of a data memory capacitor and an address selecting insulated gate field effect transistor (which will shortly be called a "MOSFET") and is stored with a data of logic values "1" and "0" in a form of whether or not the capacitor is charged. The readout of the data is conducted by turning on the address selecting MOSFET to couple the data holding capacitor to a bit or data line and by sensing how the data line has its potential changing with the quantity of the charge stored in the capacitor.
In the RAM of recent years having a high integration and a large capacity, each memory cell has its size reduced, and a large number of memory cells are coupled to each data line. In accordance with this, the relationship between the capacitance Cs of the capacitor and a stray capacitance (i.e., a data line capacitance) Co of the data line, i.e., the ratio of Cs/Co takes a very small value so that the data signal to be fed from the memory cells to the data line, namely, the potential change to be applied to the data line in accordance with the quantity of the charge stored in the capacitor Cs has a very small value.
In order to make it possible to detect the small data signal, a differential sense technique or a balanced sense technique is utilized, as is disclosed, for example, in the specification of U.S. Pat. No. 4,061,954 (Ref. 1), in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-7, No. 5, October, 1972, pp. 336 to 340 (Ref. 2) or ISSCC 84, DIGEST OF TECHNICAL PAPERS pp. 276 to 277 (Ref. 3).
In accordance with the technique disclosed above, the two data, bit or digit lines are paired, and there is coupled to the paired data lines (which will be called "complementary data lines", too) a sense amplifier which is constructed of a symmetric latch circuit for substantially conducting a differential or balanced amplification. One of the paired data lines is fed with the data signal from the memory cell, and the other is supplied with a reference potential which has an intermediate level between the high and low levels of the data signal. The reference potential is generated by the method (Ref. 1) using such a dummy cell (which will be called a "half-size dummy cell") as is made to have a capacitance half as large as that of the memory cell, by the method (Ref. 2) using such a dummy cell (which will be called a "full-size dummy cell") which has a capacitance substantially equal to that of the memory cell and as has its capacitor supplied in advance with a charge half as large as that of the memory cell, or by the precharge method (Ref. 3) (which will be called a "half-precharge method or dummy-cellless method") using a pre-short-operation between the respective data lines. The small signal level difference, which is established between the paired data lines on the basis of that reference potential, is amplified by the operation of the sense amplifier.
The reference potential has to be set at a desired level so that it enable the desired sensing operation.
Here, the half-size dummy cell is to be used, the margin of the sensing operation is highly influenced by the relative accuracy between the capacitors of the dummy cell and the memory cell. In general, the dummy cell is made under the same fabricating conditions and with the same design constants as those of the memory cell except that its capacitor has a capacitance substantially half as large as that of the capacitor of the memory cell, so that the relative accuracy between its capacitor and the capacitor of the memory cell may be enhanced.
In the dynamic RAM having a high memory capacity such as 1 mega bit, however, it becomes very difficult to fabricate a dummy cell having a half size because of the requisite small size of the data storing capacitors. In other words, the limitation and dispersion of the working accuracy of the element pattern make it difficult to fabricate the capacitor which has a capacitance substantially half as large as that of the capacitor of the memory cell.
In case the half-size dummy cell is to be used, therefore, it becomes difficult to establish the reference potential at the desired level.
In the system using the full-size dummy cell and the dummy-cellless system, on the contrary, it is possible to prepare a reference potential at a relatively accurate level. Thus, when the full-size dummy cell is used, more specifically, the dummy cell and the memory cell can be made to have the capacitors of the same size so that their relative accuracy can be sufficiently enhanced despite the working accuracy and dispersion. In the case of the dummy-cellless system, the relative accuracy of the capacitors raises no direct problem because the system has no dummy cell.
However, we have found that a reduction in the operating margin of the circuit is frequently caused by the fluctuations in the supply voltage even in the dynamic RAM of the type in which the relative accuracy of the dummy cell raises no serious problem as in the full-size dummy cell system. We also have found that the reduction in the operating margin of the circuit is also caused by the undesired change in the data line potential due to .alpha. particles.